Error Migrating Design from 11.0 to 11.0 SP1 for DDR2 and DDR3 SDRAM Controller with UniPHY - Error Migrating Design from 11.0 to 11.0 SP1 for DDR2 and DDR3 SDRAM Controller with UniPHY Description Attempts to migrate an 11.0 design to 11.0 SP1 fails and displays an error message. Resolution The workaround for this issue is to open the .v file in an editor and change the value� of CSR_ADDR_WIDTH to 8. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']