Arria V and Cyclone V Hard IP for PCIe IP Core Do Not Cycle through Gen1 and Gen2 Data Rates in CBB Testing - Arria V and Cyclone V Hard IP for PCIe IP Core Do Not Cycle through Gen1 and Gen2 Data Rates in CBB Testing Description When performing the TX Eye Test as part of the PCI Express Compliance Base Board (CBB) testing, the Arria V and Cyclone V Hard IP for PCIe do not cycle through the Gen1 and Gen2 data rates. Resolution This issue is fixed in version 13.0 of the Hard IP for PCI Express IP Cores. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 11.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']