Why does the HDMI Intel® FPGA Sink IP encounter intermittent HDMI 2.1 Rx link training failure ? - Why does the HDMI Intel® FPGA Sink IP encounter intermittent HDMI 2.1 Rx link training failure ? Description Due to a problem starting in version 19.4 of the Intel® Quartus® Prime Pro software when using Intel® Arria® 10 Devices, and version 20.4 of the Intel® Quartus® Prime Pro software when using Intel® Stratix® 10 devices the HDMI Intel® FPGA Sink IP may intermittently encounter HDMI 2.1 Rx link training failure. This problem is due to the HDMI Intel® FPGA Sink IP core does not perform symbol re-alignment correctly if the FRL lock signal becomes unstable after initial locked stage. Resolution This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 21.1 software. Custom Fields values: ['novalue'] Troubleshooting 1508828335 True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 19.4 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']