Cyclone 10 LP Error Detection Timing - Cyclone 10 LP Error Detection Timing I am working with the cyclone 10 LP FPGA dev board from Altera. I am trying to get the error detection block working during configuration. I have followed this guide: accessing-error-detection-block-through-user-logic-cyclone-10-lp I have added the cyclone 10 lp components library and was able to instantiate this WYSIWYG atom: ------------------------------------------------------------------ -- cyclone10lp_crcblock parameterized megafunction component declaration -- Generated with 'mega_defn_creator' loader - do not edit ------------------------------------------------------------------ component cyclone10lp_crcblock generic ( lpm_hint : string := "UNUSED"; lpm_type : string := "cyclone10lp_crcblock"; oscillator_divider : natural := 1 ); port( clk : in std_logic := '0'; crcerror : out std_logic; ldsrc : in std_logic := '0'; regout : out std_logic; shiftnld : in std_logic := '0' ); end component; The crc block shows up in the technology map, and I am able to shift out the pre-calculated CRC and CRC result (depending on the ldsrc value) using the regout port. the CRC_ERROR pin is also working correctly. The timing is not working correctly. Regardless of the internal oscillator divisor setting, the time from INIT_DONE pin going high to CRC_ERROR pin going low is ~240 ms. I have tried changing the divisor setting in the quartus GUI, as well as in the generic map during instantiation. I was careful to make sure both matched, however even a divisor value of 256 does not change the timing at all. According to this CRC error detection timing table, the time should be between 9 ms and 4.51 s for the 10CL025 device on the dev kit (depending on oscillator divisor). Why am I not getting any time change when I change the oscillator divisor? I have tried in both Quartus 24.1 STD and 25.1 STD Replies: Re: Cyclone 10 LP Error Detection Timing Thank you for the clarification and getting back to me. Replies: Re: Cyclone 10 LP Error Detection Timing Hello, The oscillator_divider generic does not change the CRC engine's clock. CRC is clocked by internal configuration oscillator. Instead, set the clock in device option. Device and Pin option -> Error Detection CRC -> "Divide error check frequency by"(this will impact the internal configuration oscillator that clocks the CRC engine. Valid values are power of 2. Below is the .qsf example : set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR <2|4|8|...|256> regards, Farabi Replies: Re: Cyclone 10 LP Error Detection Timing Hello, Let me check the issue and get back to you. regards, Farabi Replies: Re: Cyclone 10 LP Error Detection Timing I would like to clarify an error in my post, I am measuring the time from power on to CRC_ERROR going low. This time measurement is approximately 240 ms no matter what the divisor is.