Why does the Intel® Quartus® Prime Standard Edition Software generate compilation checksums that are not identical when the source files haven't changed? - Why does the Intel® Quartus® Prime Standard Edition Software generate compilation checksums that are not identical when the source files haven't changed? Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 16.1 and later, the non-deterministic fitter results may have different compilation checksums even after a clean project or removing db and incremental_db directories between compiles. This problem impacts designs that contain IP that utilize the JTAG-related debug features, for example, In-System Sources and Probes, Signal Tap, EMIF IP with debug, and so on. Resolution To work around this problem in the Intel® Quartus® Prime Standard Edition Software version 16.1 and later, pre-generate a ll IP in the project before performing the first compile. Example: qsys-generate InSystemSignalsProbesIP.qsys --synthesis=VERILOG --output-directory= InSystemSignalsProbesIP --family="Arria 10" --part=10AX115N1F45I1SGqsys-generate DDR4x16_IP.qsys --synthesis=VHDL --output-directory=DDR4x16_IP --family="Arria 10" --part=10AX115N1F45I1SG Note: If using the Intel® Arria® 10 device, it is recommended to migrate to the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 1409949138 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 16.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']