Why does the F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to pass 100% of packets when the “MAC Client Loopback Mode” button is selected in the Ethernet Toolkit? - Why does the F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to pass 100% of packets when the “MAC Client Loopback Mode” button is selected in the Ethernet Toolkit? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3, the F-Tile Ethernet Intel® FPGA Hard IP design example cannot pass 100% of packets when using the “MAC Client Loopback Mode” in the Ethernet Toolkit. Resolution There is no workaround for this problem in version 21.3. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14015598292 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']