Why do I get a simulation error “wr_data is X” for the F-Tile Ethernet FPGA Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled? - Why do I get a simulation error “wr_data is X” for the F-Tile Ethernet FPGA Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and 24.2, you may see an error “ wr_data is X ” during simulation for F-Tile Ethernet FPGA Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled. While running the simulation, this error occurs for the 25GE-1 variant with the “MII PCS only” Client Interface example design. Resolution To work around this problem, perform the following steps: ) Navigate to <your_design_path>/example_testbench folder ) Open “ basic_avl_tb_top.sv ” testbench file ) Add ~20us delay for the de-assertion of " i_reconfig_reset " as shown below ) Run the simulation as explained in the Design Example User Guide. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 16024331336 False ['F-Tile Auto-Negotiation and Link Training for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']