Why does the configuration time for Intel Agilex® 7 devices increase around 10% when using 4 transceiver tile (F-tile/R-tile) in the design in Intel® Quartus® Prime Pro Edition Software Version 23.4? - Why does the configuration time for Intel Agilex® 7 devices increase around 10% when using 4 transceiver tile (F-tile/R-tile) in the design in Intel® Quartus® Prime Pro Edition Software Version 23.4? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.4, you may observe that the configuration time for Intel Agilex® 7 devices increases by around 10% compared to previous versions when using 4 transceiver tiles (F-tile/R-tile) in the design. Resolution This problem will be fixed in a future release of Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16022622163 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['Altera® FPGA Programming Software'] ['novalue'] ['novalue']