Why is the interrupt signal on 16550 Compatible UART Intel® FPGA IP asserted right after reset releases? - Why is the interrupt signal on 16550 Compatible UART Intel® FPGA IP asserted right after reset releases? Description Due to a problem with Intel® Quartus® Prime Standard Edition Software version 21.1 and 21.1.1, ier_dlh Interrupt signals on 16550 Compatible UART Intel® FPGA IP are asserted right after reset releases. Resolution To work around this problem, there are two options: 1. Use Intel® Quartus® Prime Standard Edition Software version 22.1 or later versions because the problem has been fixed in Intel® Quartus® Prime Standard Edition Software version 22.1. 2. Read rbr_thr_dll register, then the interrupt signal will be cleared. Custom Fields values: ['novalue'] Troubleshooting 15013566709 False ['16550 Compatible UART IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 22.1 21.1 ['Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 Bare Die', 'Cyclone® 10 LP FPGA', 'MAX® CPLDs', 'Stratix® FPGAs', 'Stratix® II FPGAs', 'Stratix® III FPGAs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']