Synthesis fails with "Error (10170): Verilog HDL syntax error..." for designs using debug instrumentation to the Qsys interconnect - Synthesis fails with "Error (10170): Verilog HDL syntax error..." for designs using debug instrumentation to the Qsys interconnect Description In the Quartus II software release version 14.1, synthesis fails for designs using Qsys interconnect instrumentation. The Quartus II software will display an error similar to the following: Error (10170): Verilog HDL syntax error at <qsys system name>_mm_interconnect_0_monitor_m_0_master_gatherer.sv(423) near text "-" Resolution You must use the Quartus II software release version 13.1 or 14.0 if using debug instrumentation to the Qsys interconnect. This issue will be fixed in a future software release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']