Why doesn't the Soft IP PCIe* core send my Avalon®-MM memory read request to PCIe* bus? - Why doesn't the Soft IP PCIe* core send my Avalon®-MM memory read request to PCIe* bus? Description Due to a bug in Soft IP PCIe* generated by SOPC builder, the core may not send memory read request (MRD) to PCIe* bus although it is presented correctly on Avalon®-MM interface. This issue does not affect Soft IP with Avalon®-ST interface or any Hard IP PCIe* cores. If you are using Quartus® II software version 10.1, you can download download and install the following patch to resolve this issue. Download the Download the Quartus II software version 10.1 Patch 0.13 for Windows (.exe) Download the Download the Quartus II software version 10.1 Patch 0.13 for Linux (.tar) Download the Readme for the Quartus II software Download the Quartus II software version 10.1 Patch 0.13 (.txt) Currently there is no workaround for earlier Quartus® II software versions. If using an earlier version of the Quartus® II tools, Intel® recommend moving to Quartus® II version 11.0 software. Custom Fields values: ['novalue'] Troubleshooting 361722 False ['IP Compiler for PCI Express'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.1 ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Cyclone® IV GX FPGA', 'Stratix® GX FPGA', 'Stratix® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']