Why do I see an Intel® Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY Intel® FPGA IP as FGT, System PLL Clocking mode, single width, 16-bit PMA interface? - Why do I see an Intel® Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY Intel® FPGA IP as FGT, System PLL Clocking mode, single width, 16-bit PMA interface? Description Due to a bug in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier, you may see a Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY Intel® FPGA IP as FGT, System PLL Clocking mode, single width, 16 bit PMA interface. The Intel Quartus Logic Generation Error will contain the following: Error(21843): sys_clk_src == SYS_CLK_SRC_XCVR Error(21843): tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_REGISTER Error(21843): tx_en == TRUE Error(21843): tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_PHASECOMP Error(21843): tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE Error(21843): tx_xcvr_width == TX_XCVR_WIDTH_16 Resolution To work around this error, perform the steps below: 1. Open the *.tlg.rpt file in the output_files folder 2. Search for "bb_f_ehip_tx" and "bb_f_ehip_rx" under the "Logic Generation Tool IP Parameter Settings Report" section of the .tlg.rpt file, and copy the paths associated with bb_f_ehip_tx and bb_f_ehip_rx. The two respective values will look similar to the following example: fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx -entity top_devkit fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx -entity top_devkit 3. Add the following two Quartus Settings File (QSF) assignments with the <value> field being the two respective paths copied in step 2 set_instance_assignment -name HSSI_PARAMETER "tx_primary_use=TX_PRIMARY_USE_BUNDLE_SOFT_PIPE" -to <value> set_instance_assignment -name HSSI_PARAMETER "rx_primary_use=RX_PRIMARY_USE_BUNDLE_SOFT_PIPE" -to <value> The complete QSF assignment will look similar to the following example: set_instance_assignment -name HSSI_PARAMETER "tx_primary_use=TX_PRIMARY_USE_BUNDLE_SOFT_PIPE" -to fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx -entity top_devkit set_instance_assignment -name HSSI_PARAMETER "rx_primary_use=RX_PRIMARY_USE_BUNDLE_SOFT_PIPE" -to fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx -entity top_devkit 4. Save the QSF and compile the design . This problem will be fixed in a future release of the Intel® Quartus Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14017028835 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.3 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']