Why does the Intel® Stratix® 10 SoC FPGA Hard Processor System hang after a warm reset or watchdog warm reset? - Why does the Intel® Stratix® 10 SoC FPGA Hard Processor System hang after a warm reset or watchdog warm reset? Description The Intel® Stratix® 10 SoC FPGA Secure Device Manager(SDM) is not able to bring the HPS out of warm or watchdog reset after a reconfiguration. Additionally, if a warm reset or watchdog warm reset has occurred, any subsequent attempt to reconfigure the device may fail. Resolution Please use the Intel Quartus™ Prime Pro Edition Software version 18.1 build 222 with patch 0.01, available at: quartus-18.1-0.01dp1-linux.run quartus-18.1-0.01dp1-windows.exe Custom Fields values: ['novalue'] Troubleshooting 2205699600, 1408179856, 1408205534 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.1 ['Stratix® 10 SX FPGA'] ['Embedded Dev Tools SoC Suite'] ['novalue'] ['novalue']