Why does my RiscFree fail to run debug using the Nios® V "GSFI Bootloader Example Design"? - Why does my RiscFree fail to run debug using the Nios® V "GSFI Bootloader Example Design"? Description In the RiscFree IDE for Intel® FPGAs software version 22.2 and earlier, you may see " 'Launching app.elf' has encountered a problem." "Error in GDB server launch sequence" or " Error occurred during enumeration of RISC-V harsts (no harts found)." Resolution This problem is scheduled to be fixed in a future release of the RiscFree* IDE for Intel® FPGAs. Custom Fields values: ['novalue'] Troubleshooting 15012144385 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.2 ['Agilex™ 7 FPGA F-Series', 'Arria® 10 SX FPGA', 'Cyclone® 10 FPGAs', 'Stratix® 10 AX FPGA', 'Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']