Why is the addressing incorrect for the CRA port on the Hard IP for PCI Express? - Why is the addressing incorrect for the CRA port on the Hard IP for PCI Express? Description The Qsys address translation for the CRA port on the Avalon®-MM Hard IP for PCI Express® is incorrect when using VHDL as the generation language. This problem does not occur when using Verilog HDL. Resolution To work around this problem in VHDL, manually edit the generated VHDL file: Open the Qsys <top level>.vhd file, identify the altpcie_< device family>_hip_avmm_hwtcl component. Change the line from: CraAddress_i : in std_logic_vector(11 downto 0) to CraAddress_i : in std_logic_vector(13 downto 2) This problem is scheduled to be fixed in a future version of the Quartus® II software. Related Articles Why is my Stratix IV Hard IP for PCI Express VHDL altpcierd_write_dma_requester_128.vhd different from its Verilog counterpart? Why do memory reads and writes fail to my PCI Express Endpoint enabled BAR locations? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']