Why the Fmax of OpenCL™ design on the Intel® Programmable Acceleration Card D5005 may be far lower than that of the Intel® Stratix® 10 GX FPGA Development Kit？ - Why the Fmax of OpenCL™ design on the Intel® Programmable Acceleration Card D5005 may be far lower than that of the Intel® Stratix® 10 GX FPGA Development Kit？ Description When you compile the OpenCL™ example design “matrix_mult” on the Intel® Programmable Acceleration Card D5005(D5005), you may find the kernel Fmax is far lower than the Intel® Stratix® 10 GX FPGA Development Kit(S10 GX Dev Kit). For example, the fmax on your design can reach 424MHz on the S10 GX Dev Kit, but only 300MHz on the Intel® Programmable Acceleration Card D5005. One of the reasons for the lower Fmax is that D5005 Card has four DDR banks and S10 GX Dev Kit has only one DDR bank. Another reason is the D5005 OpenCL™ Board Support Package (BSP) has some optimizations missing that the S10 GX BSP uses. Resolution This problem is scheduled to be fixed in a future release of the Intel® Acceleration Stack for Intel Xeon® CPU with FPGAs. Custom Fields values: ['novalue'] Troubleshooting 1507505049 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1.2 ['Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']