Why does the F-Tile Low Latency Ethernet 10G MAC FPGA IP show the target development kit as a P-Tile and E-Tile board? - Why does the F-Tile Low Latency Ethernet 10G MAC FPGA IP show the target development kit as a P-Tile and E-Tile board? Description Due to a problem in the Quartus® Prime Pro Edition Design Software Version 24.2, the F-Tile Low Latency Ethernet 10G MAC FPGA IP GUI Example Design tab shows the target board as Agilex™ 7 FPGA F-Series Development Kit (Production P-Tile and E-Tile) when the target is an F-Tile based device. Resolution This problem is fixed in version 24.3 of the Quartus® Prime Pro Edition Design Software. Custom Fields values: ['novalue'] Troubleshooting 16024634809 False ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.2 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']