Why does the Arria® 10 Multi-Rate Ethernet PHY IP in USXGMII Auto-Negotiation mode fail in simulation? - Why does the Arria® 10 Multi-Rate Ethernet PHY IP in USXGMII Auto-Negotiation mode fail in simulation?
Description The Arria® 10 Multi-Rate Ethernet PHY IP default value of usxgmii_link_timer at register address 0x412 is 0x7c000 . This default reset value sets the link timer to 1.6ms, which is too long in simulation. Resolution To work around this problem, set usxgmii_link_timer bit[19:14]=0x01 at address 0x412 to speed up the auto-negotiation process for simulation. This change sets usxgmii_link_timer to the fastest link timer value possible in this register i.e. 0.05ms.
Custom Fields values:
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Troubleshooting
1408201100; FB: 478754;
False
['1G 2.5G 5G 10G Multi-rate Ethernet PHY IP', 'Ethernet 10G MAC IP', 'Low Latency Ethernet 10G MAC IP']
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['Arria® 10 FPGAs and SoCs']
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['novalue'] - 2024-10-14
external_document
- Resource Type
- Support Resources > Knowledge Articles
- Source Name
- khoros