Creating Reusable Design Blocks: IP Design & Implementation with the Altera® Quartus® Prime Software - Same Course in Japanese: 再利用可能なデザイン・ブロックの生成方法：IPデザインとその実装 29 Minutes This training is part 2 of 3. As FPGA designs get larger and more complicated, intellectual property (IP) is being used more often to help reduce time-to-market. Including IP allows designers to focus on new aspects of their design and improve existing designs instead of spending time recreating what’s been done before. But what if you want to create your own IP? This training focuses on all aspects of how to create good reusable IP, including the IP user flow, the creation of IP files, the packaging of the IP, as well as other important factors to consider during the creation process. Course Objectives At course completion, you will be able to: Create IP that works within the typical IP user flow Follow recommended packaging techniques, including file and signal naming conventions Manage the creation and use of parameters for IP customization Skills Required Background in digital logic design Familiarity with an HDL language (Verilog or VHDL) Familiarity with the Altera® Quartus® Prime software Familiarity with Tcl scripting Some familiarity with SDC timing constraints If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OIPR1001. FPGA_OIPR1001. <p>Creating Reusable Design Blocks: IP Design & Implementation with the Altera Quartus Prime Software</p>