University Self-Guided Lab: Introduction to Simulation and Debug of FPGAs - 38 Minutes This online course consists of a 40 minute lecture and demonstrations and roughly two hours of self-guided laboratory exercises to learn the fundamentals of logic simulation and FPGA debugging tools available in the Quartus FPGA development tools using the Terasic DE10-Lite development kit. The laboratory exercises give the student hands on experience with ModelSim simulation, In-system Sources and Probes, and the Signal Tap in-chip logic analyzer. You will need to acquire the DE10-Lite development board from Terasic’s website or from electronic distributors such as Mouser or Digikey. The lab manual can be found in the resources section of this online class. Course Objectives At course completion, you will be able to: Understand the fundamental processes for Simulating a design and debugging Use ModelSim to effectively simulate designs and identify faults in it Use In-system Sources and Probes to probe at nodes in design and be able to observe hardware problem live Use Signal Tap Logic Analyzer to be able to trigger events from clock edges and analyze those events as they happened in hardware Skills Required Basic understanding of Boolean combinational logic and sequential logic Minimal experience in a software language such as C, Java, or Python If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OUWSDBUG. FPGA_OUWSDBUG. <p>University Self-Guided Lab: Introduction to Simulation and Debug of FPGAs</p>