Why do I see bit errors with my DDR3 controller? - Why do I see bit errors with my DDR3 controller? Description You may see bit errors with your DDR3 UniPHY memory controller if the REFRESH command period, tRFC, is set too low. Resolution The memory controller could perform READ or WRITE commands before the REFRESH cycle has completed causing the corruption of data. Make sure to set the tRFC timing parameter in the Megawizard GUI to the correct value specified in the memory device datasheet. Custom Fields values: ['novalue'] Troubleshooting 1408030190 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']