Why does the Bursting Avalon -MM Master (BAM) interface of the Avalon-MM Intel® Stratix® 10 Hard IP for PCI* Express and the Intel P-Tile Avalon® -MM IP for PCI* Express have incorrect address ? - Why does the Bursting Avalon -MM Master (BAM) interface of the Avalon-MM Intel® Stratix® 10 Hard IP for PCI* Express and the Intel P-Tile Avalon® -MM IP for PCI* Express have incorrect address ? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.3, when Intel® P-Tile/H-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express is configured with multiple BARs of different size, BAM upper address is not correctly masked according to the BAR size. If the system does not align BARs physical address to the highest BAR size, the address field on the user side size will be incorrect. For example for BAR0: 64KB and BAR2: 1MB, system assigns the following physical address: F021000 for BAR0 F020000 for BAR2 BAM address is 20 bits When system issues a write or read request targeting BAR0 offset 0x800, BAM interface will output address 0x10800 instead of 0x00800 Resolution To work around this problem for the Intel® Quartus® Prime Pro Edition software version 19.3 and 19.4, application can externally implement the address masking using BAM BAR conduit (bam_bar_o) and BAR size. For above example: assign bam_address_fix = (bam_bar_o== 3'b000) ? {4'b0, bam_address_o [15:0]} : bam_address_o; This problem is fixed in the Intel® Quartus® Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 14010246417 True ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.3 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']