How do I ensure consistent behavior between Avalon-MM and Avalon-ST PCIE HIP in the Arria V or Cyclone V device families? - How do I ensure consistent behavior between Avalon-MM and Avalon-ST PCIE HIP in the Arria V or Cyclone V device families? Description For the Arria® V and Cyclone® V device families, to ensure consistent behavior between the Avalon®-MM and Avalon-ST PCI Express® Hard IP, 2 parameters need to be changed from the Avalon-MM wrapper to match the default values in the Avalon-ST wrapper. Resolution In the file altpcie_sv_hip_avmm_hwtcl.v , look for the following parameter definitions near the top of the file (around line 148) and make the changes identified: parameter rx_cdc_almost_full_hwtcl = 6, parameter tx_cdc_almost_full_hwtcl = 6, Change to: parameter rx_cdc_almost_full_hwtcl = 12, parameter tx_cdc_almost_full_hwtcl = 12, Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1 11.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']