A10SOC: "SPI FPGA IP"'s Interrupt Sender is "7", but in linux Device Tree "irqno" set to “26” ？Why - A10SOC: "SPI FPGA IP"'s Interrupt Sender is "7", but in linux Device Tree "irqno" set to “26” ？Why I'm studying an A10SOC FPGA Project from ADI. In the QSYS Designer, there's an "INTEL FPGA SPI IP" module, its IRQ NUMBER set is to "7" (as below picture). And this spi irq connects to "f2h_irq0" of SYS_HPS. But checking linux device tree, the "sys_spi" device says as following: sys_spi: spi@40 { compatible = "altr,spi-1.0"; reg = <0x00000040 0x00000020>; interrupt-parent = <&intc>; interrupts = <0 26 4>; // => in linux device tree, the "interrupt no" is set to 26, WHY ?? . #address-cells = <0x1>; #size-cells = <0x0>; }; Pls help to clarify How this " 26 " comes from ? Thanks Replies: Re: A10SOC: "SPI FPGA IP"'s Interrupt Sender is "7", but in linux Device Tree "irqno" set to “26” ？Why Thanks @Isaac_V_Intel for the answer, I search and found there's the explaination as following on rocketboard , " .. It is worth noting that the GIC IRQ computation for FPGA based peripherals is slightly different for A10 SoC . Unlike CV SoC , the A10 SoC requires us to add 51 to the IRQ value reported in the Platform Designer header and then subtract 32 from that value " ( https://rocketboards.org/foswiki/Documentation/HOWTOCreateADeviceTree ) Appreciate your clarification Replies: Re: A10SOC: "SPI FPGA IP"'s Interrupt Sender is "7", but in linux Device Tree "irqno" set to “26” ？Why Hello. The "26" is because you have the interruption vector with 32 irq, also the irq have the 51 position. So, in the Linux case, you need to make the correct offset for the system understanding. Here is how the macro calculate the offset: #define BUTTON_PIO_IRQ (A10_HPS_BUTTON_PIO_IRQ + 51 - 32) Best regards, Isaac Vazquez.