Introduction to Incremental Compilation in the Altera® Quartus® Prime Standard Edition Software - Same Course in Simplified Chinese: 渐进式编译入门 184 Minutes You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature of the Quartus® II software, now known as the Altera® Quartus Prime Standard Edition software. By the end of this training, you will be able to use LogicLock™ regions to physically partition (floorplan) your design. You will be able to decide when and when not to use incremental compilation, how best to set up your design hierarchy and source code to support incremental compilation, and how to segment your design into logical design partitions. You will also be able to apply the incremental compilation methodology to both the top-down and team-based design flows. Course Objectives At course completion, you will be able to: Create & Manage LogicLock regions to physically partition a design Create & Manage good design partitions Determine whether your next design can benefit from incremental compilation Set up & perform incremental compilation Use incremental compilation in the top-down & team-based design flows Set up a top-level project framework with constraints for a team-based design flow Generate design partition scripts Export a lower-level design & import it into the top-level design Skills Required Background in digital logic design Familiarity with using the Quartus II software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSW1136. FPGA_ODSW1136. <p>Introduction to Incremental Compilation in the Altera Quartus Prime Standard Edition Software</p>