Transceiver PHY IP Support Center - The Transceiver PHY IP Support Center provides information on how to select, design, and implement Transceiver PHY IP links. Information on how to select, design, and implement Transceiver PHY IP links. Design Pages {"title":"Transceiver PHY IP Support Center"} The Transceiver PHY IP support center provides information on how to select, design, and implement transceiver links for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish. Get additional support for Agilex™ 7 FPGA Interface Protocol Design , Agilex™ 5 FPGA Interface Protocol Design , and Agilex™ 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation. For other devices, search the Device and Product Support Collections . Getting Started Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series Agilex™ 7 FPGAs and SoCs Device Overview Agilex™ 7 Device Design Guidelines E-Tile Transceiver PHY User Guide F-Tile Ethernet FPGA Hard IP User Guide Agilex™ 5 FPGAs and SoCs Device Overview Agilex™ 5 FPGAs and SoCs Device Data Sheet Agilex™ 3 FPGAs and SoCs Device Overview Agilex™ 3 FPGAs and SoCs Device Data Sheet Getting Started 1. Device and IP Selection 1. Device and IP Selection Which FPGA Device Family Should I Use? Table 1 - Device Variant Maximum Transceiver Data Rate and Channel Count Feature Support Device Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 Device Variant F-Series E-Tile D-Series E-Series (Group A) E-Series (Group B) C-Series GX/SX L-Tile GX/SX H-Tile MX/TX E-Tile SX 3, 5 GX 3, 5 GT 4 GX Maximum Data Rate (Chip-to-Chip) 1, 6 GX Channels - - - - - - 17.4 Gbps - 17.4 Gbps 17.4 Gbps 17.4 Gbps 12.5 Gbps GXT Channels - - - - - 26.6 Gbps 28.3 Gbps 28.3 Gbps - - 25.8 Gbps - GXE Channels 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) - - - - - - 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) - - - - GTS Channels - 28.1 Gbps 28.1 Gbps 17.16 Gbps 12.5 Gbps - - - - - - - Maximum Data Rate (Backplane) 7 GX Channels - - - - - 12.5 Gbps 28.3 Gbps 28.3 Gbps 12.5 Gbps 12.5 Gbps 12.5 Gbps 6.6Gbps GXT Channels - - - - - 12.5 Gbps 28.3 Gbps 28.3 Gbps - 12.5 Gbps 12.5 Gbps - GXE Channels 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) - - - - - - 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) - - - - GTS Channels - 28.1 Gbps 28.1 Gbps 17.16 Gbps 12.5 Gbps - - - - - - - Maximum Channels per device GX Channels - - - - - 96 96 - 96 72 72 12 GXT Channels - - - - - 32 64 24 - 6 6 - GXE Channels 24 (and 32 P-Tile) - - - - - - 120 - - - - GTS Channels - 32 24 24 4 - - - - - - - Notes: The values shown in the table above are for standard power modes. In reduced power mode, the maximum data rate for Arria® 10 GX device channels (chip-to-chip) is 11.3 Gbps. As the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. For more details, refer to the Arria® 10 Device Datasheet. Arria® 10 and Stratix® 10 device transceivers can support data rates below 1.0 Gbps through over sampling. For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade. Refer to the Device Datasheet for lower speed grade specifications. For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade. Refer to the Device Datasheet for the lower speed grade specifications. Stratix® 10 device transceivers have both GX and GXT types of transceiver channels. For details, refer to the Stratix® 10 L-/H-Tile Transceiver PHY User Guide. Arria® 10 and Stratix® 10 device transceivers can support data rates below 1.0 Gbps through over sampling. Backplane applications refer to the ones that require advanced equalization, such as decision feedback equalization (DFE) enabled to compensate for channel loss. Table 2 - Interface Hard IP Device Variant and Feature Support Device Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 Device Variant F-Series E-Tile D-Series E-Series (Group A) E-Series (Group B) C-Series GX/SX L-Tile GX/SX H-Tile MX/TX E-Tile SX GX GT GX PCIe Hard IP One PCIe Gen2 x4 per device. Up to four PCIe 4.0 x8 Up to six PCIe 4.0 x4 Up to six PCIe 3.0 x4 or PCIe 4.0 x4 2 One PCIe 3.0 x4 PCIe Gen3 x16 up to 4 per device - - PCIe Gen3 x16 up to 4 per device PCIe Gen3 x16 up to 4 per device PCIe Gen3 x16 up to 4 per device PCIe* Gen3 x8 up to 4 per device Ethernet Hard IP 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514) 10G/25G Ethernet with optional 1588 PTP capability + Firecode FEC/RS-FEC (528, 514) 10G/25G Ethernet with optional 1588 PTP capability + Firecode FEC/RS-FEC (528, 514) 10G Ethernet with optional 1588 PTP capability + Firecode FEC 10G Ethernet with optional 1588 PTP capability + Firecode FEC - 50/100 Gbps Ethernet MACup to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF) 1 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514) - - - - USB 3.1 Hard IP 3 - One channel with USB 3.1 controller in HPS block One channel with USB 3.1 controller in HPS block One channel with USB 3.1 controller in HPS block One channel with USB 3.1 controller in HPS block - - - - - - - Notes: SR-IOV stands for Single-Root Input Output Virtualization. Supported for -4s speed grade (VCC=0.8V) devices only. The hardened USB 3.1 IP controller resides in the HPS block, and is supported for devices with GTS transceiver and HPS only. FPGA Device Datasheets Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series Agilex™ 5 FPGAs and SoCs Device Data Sheet Agilex™ 3 FPGAs and SoCs Device Data Sheet Stratix® 10 Device Datasheet Arria® 10 Device Datasheet Cyclone® 10 GX Device Datasheet Additional Resources Topic Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 Additional Resources E-Tile transceiver PHY user guide GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs Stratix® 10 L- and H-Tile transceiver PHY user guide E-Tile transceiver PHY user guide AN 778 - Stratix® 10 transceiver usage Arria® 10 transceiver PHY user guide Cyclone® 10 transceiver PHY user guide 2. Design Flow and IP Integration Where Can I Find Information on Transceiver Usage? AN 778: Stratix ® 10 transceiver usage E-Tile channel placement tool F-Tile Channel Placement Tool Use the E-Tile Channel Placement Tool in conjunction with the Stratix ® 10 Device Family Pin Connection Guidelines, to swiftly plan protocol placements in the E-Tile prior to reading comprehensive documentation and implementing designs in the Quartus® Prime software. The Excel-based E-Tile Channel Placement Tool is supplemented with instruction, legend, revision, and protocols tabs. 2. Design Flow and IP Integration Topic Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 What Design Recommendations Should I Consider? AN 886: Agilex™ 7 device design guidelines Device Design Guidelines: Agilex™ 5 FPGAs and SoCs Device Design Guidelines: Agilex™ 3 FPGAs and SoCs Stratix® 10 device design guidelines Arria® 10 GX/GT device errata and design recommendations Arria® 10 SX device errata and design recommendation Cyclone® 10 GX device errata and design guidelines Where Can I Find Information on Transceiver PHY IP Integration? E-Tile transceiver PHY user guide Agilex™ 7 Clocking and PLL User Guide GTS Transceiver PHY User Guide GTS Transceiver PHY User Guide Stratix® 10 L- and H-Tile transceiver PHY user guide E-Tile transceiver PHY user guide Arria® 10 transceiver PHY user guide AN 738: Arria® 10 device design guidelines Cyclone® 10 GX Transceiver PHY User Guide Cyclone® 10 GX Device Design Guidelines Where Can I Find Information on Transceiver PHY IP Register Mapping? F-Tile Auto-Negotiation and Link Training FPGA IP Register Map F-Tile PMA and FEC Direct PHY FPGA IP Register Map GTS PMA/FEC Direct PHY FPGA IP Register Map for Agilex™ 5 GTS PMA/FEC Direct PHY IP Register Map for Agilex™ 3 Logical view of the Stratix® 10 L- and H-Tile transceiver registers Logical view of the Arria® 10 transceiver registers Logical view of the Cyclone® 10 transceiver registers Analog Settings Guidelines Stratix® 10 L-Tile/H-Tile pre-emphasis and output swing estimator Arria® 10 pre-emphasis and output swing estimator Cyclone® 10 and Arria® 10 pre-emphasis and output swing estimator 3. Board Design and Power Management 3. Board Design and Power Management Topic Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 Max® 10 Stratix® V Arria® V Cyclone® V Max® V Board Design Guidelines Agilex™ 7 Configuration User Guide Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines AN 114: Board Design Guidelines for FPGA Device Packages GTS Transceiver Dual Simplex Interfaces User Guide AN 114: Board Design Guidelines for FPGA Device Packages PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex 3 FPGAs and SoCs AN 766: Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for FPGA Device Packages PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for FPGA Device Package PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for FPGA Device Packages PCB Stackup Design Considerations for FPGAs AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission AN 114: Board Design Guidelines for FPGA Device Packages PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for FPGA Device Packages AN 114: Board Design Guidelines for FPGA Device Packages PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for FPGA Device Packages PCB Stackup Design Considerations for FPGAs Pin Connection Guidelines Agilex™ 7 Device Family Pin Connection Guidelines Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs Stratix® 10 Device Family Pin Connection Guidelines Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines Cyclone® 10 GX Device Family Pin Connection Guidelines Schematic Review Agilex™ 7 Device Schematic Review Worksheet: F-Series and I-Series Agilex™ 7 Device Schematic Review Worksheet: M-Series Agilex™ 5 Device Schematic Review Worksheet: D-Series and E-Series Stratix® 10 Device Schematic Review Worksheet Arria® 10 GX, GT, and SX Schematic Review Worksheet Cyclone® 10 GX Schematic Review Worksheet Power Management Agilex™ 7 Power Management User Guide: F-Series and I-Series Thermal Modeling with the FPGA Power and Thermal Calculator AN 692: Power Sequencing Considerations for Agilex™ 7 Devices Power Management User Guide: Agilex™ 5 FPGAs and SoCs Power Management User Guide: Agilex™ 3 FPGAs and SoCs Early Power Estimator (EPE) and power analyzer AN 692: Power Sequencing Considerations for Stratix® 10 Devices AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) tool 2.0 user guide Early Power Estimator (EPE) and power analyzer AN 692: Power Sequencing Considerations for Arria® 10 Devices AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) tool 2.0 user guide Early Power Estimator (EPE) and power analyzer AN 692: Power Sequencing Considerations for Cyclone® Devices AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) tool 2.0 user guide Early Power Estimator (EPE) and power analyzer AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) tool 2.0 user guide Device-Specific Power Deliver Network (PDN) tool 2.0 user guide Early Power Estimator (EPE) and power analyzer AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) tool 2.0 user guide Device-Specific Power Deliver Network (PDN) tool 2.0 user guide Early Power Estimator (EPE) and power analyzer Simulation Models & Tools Advanced Link Analyzer The Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation. Models Advanced Link Analyzer User Guide IBIS Models for FPGA Devices SPICE Models for FPGAs Development Kit User Guides Topic Agilex™ 7 Stratix® 10 Arria® 10 Development Kit User Guides Agilex™ 7 F-Series FPGA Development Kit User Guide Agilex™ 7 F-Series Transceiver-SoC Development Kit User Guide Stratix® 10 Development Kit User Guide Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide Arria® 10 Development Kit User Guide Arria® 10 SoC Development Kit User Guide Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide 4. Interoperability and Standards Testing 4. Interoperability and Standards Testing Topic Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 Max® 10 Applications Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series PHY Lite for Parallel Interfaces FPGA IP Core Release Notes PHY Lite for Parallel Interfaces FPGA IP Core Release Notes PHY Lite for Parallel Interfaces FPGA IP Core Release Notes PHY Lite for Parallel Interfaces FPGA IP Core Release Notes PHY Lite for Parallel Interfaces FPGA IP Core Release Notes PHY Lite for Parallel Interfaces FPGA IP Core Release Notes General-Purpose I/O User Guide General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs AN 835: PAM4 signaling fundamentals LVDS SERDES User Guide LVDS SERDES User Guide: Agilex™ 3 FPGAs and SoCs AN 846: Stratix® 10 forward error correction Models IEEE 1149.6 BSDL files IEEE 1149.6 BSDL files IEEE 1149.6 BSDL files IEEE 1149.6 BSDL files IEEE 1149.6 BSDL files IEEE 1149.6 BSDL files IEEE 1149.6 BSDL files 5. Design Examples and Reference Designs 5. Design Examples and Reference Designs Topic Agilex™ 5 Arria® 10 Design Examples and Reference Designs Altera Example Designs on GitHub Terasic DE10 Advanced with Arria® 10 SoC Board ACHILLES Instant Development Kit with Arria® 10 FPGA SoM Starter Board 6. Training Courses and Videos Recommended Training Courses 6. Training Courses and Videos Topic Description E-Tile Clocking Learn about the reference clocks available on the E-tile, and E-tile transceiver datapath clocks are generated and distributed. GTS Transceiver Basics Training This training introduces the basics of the Agilex™ 5 and Agilex 3 FPGA GTS transceiver is optimized for a wide range of applications in markets such as broadcasting, industrial, medical and communications, to name a few. This course will introduce you to the GTS transceivers and the building blocks that make up them. Transceiver Toolkit Training This online training will introduce you to the Transceiver Toolkit found in the Quartus® Prime Pro software and features like Auto Sweep and the Eye Viewer. Transceiver Basics for 20 nm and 28 nm Devices Learn the basic building blocks that are found in 20 and 28 nm FPGA transceivers used to support a range of high-speed protocols. Stratix® 10 Transceiver Basics Learn the basic building blocks that are found in Stratix® 10 FPGA transceivers used to support a range of high-speed protocols. Building an Stratix® 10 FPGA Transceiver PHY Layer Learn how to define the three resources that make up an Stratix® 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller. Generation 10 Transceiver Clocking Learn the clocking resources that are found in Arria® 10 and Cyclone® 10 FPGA transceiver blocks. Other Training Courses Transceiver training courses Recommended Videos Topic Description F-Tile Channel Placement Tool The F-Tile Channel Placement Tool, in conjunction with the Device Family Pin Connection Guidelines, allows you to swiftly plan protocol placements in the product prior to reading comprehensive documentation and implementing designs in Quartus® Prime Pro software. FPGA Quick Videos Title Description 17G Transceiver Demo Video Watch the first Agilex™ 5 FPGA E-Series Group B devices running 17Gbps transceivers in our lab. Arria® 10 Device Configuration of a Simplex Transceiver Watch this video to learn how to place an Arria® 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel. Dynamic Reconfiguration of an Arria® 10 Device Transceiver Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Arria® 10 devices. How to Use the Transceiver Toolkit Part 1 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver. How to Use the Transceiver Toolkit Part 2 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver. How to Use the Transceiver Toolkit Part 3 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver. How to Use the Transceiver Toolkit Part 4 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver. Arria® 10 Transceivers: Pre-Emphasis Basics Learn the basics of the Arria® 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements. Performing Dynamic Reconfiguration for the Arria® 10 Device Transceiver Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Arria® 10 devices. Reconfigure Arria® 10 Device Transceivers Using Embedded Streamer Watch this video to learn how to perform dynamic reconfiguration with the Arria® 10 device transceiver Standard PCS using the embedded streamer. Use the IBIS-AMI Model to Estimate Signal Integrity of Arria® 10 Device Transceiver Watch this video to learn how to perform a signal integrity simulation with the Arria® 10 device transceiver IBIS-AMI model in the Advanced Link Analyzer. Additionally, this video covers eye diagram reporting. 7. Debug Tools Agilex™ 7 F-Series Device and Stratix® 10 Device E-Tile Channel Placement Tool Download User Guide 7. Debug Agilex™ 5 Device Clocking and Datapath Tool Download User Guide Agilex™ 5 Device TX Equalizer Tool Download User Guide Agilex™ 3 Device Clocking and Datapath Tool Download User Guide Agilex™ 3 Device TX Equalizer Tool Download User Guide Stratix® 10 Device E-Tile Transceiver Debug Tool The debug tool consists of two sub-tools Status tool enables you to read and reset PMA parameters and log it in a file. It also enables you to perform adaptation flow (Internal/external loopback, initial adaptation), read and reset bit errors. Tuning tool enables you to tune the transceiver with base line PMA parameter configurations for 10Gbps/28Gbps/56Gbps and with custom parameters it enables you to sweep PMA parameters and log it in a file. Use this tool to analyze the health of the transceiver channels in your Stratix® 10 Device E-Tile. Download User Guide Stratix® 10 Device L-Tile/H-Tile Transceiver PHY Debug Tool This debug tool consists of four sub-tools: Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register Eye debug tool enables you to measure the eye height and/or eye width Use this tool to analyze the health of the transceiver channels in your Stratix® 10 Device L-Tile/H-Tile Download Tool Tutorial Arria® 10 Device Transceiver PHY - Fault Tree Analyzer This interactive fault tree analyzer provides guidelines for troubleshooting issues you may encounter while using Arria® 10 Device Transceiver PHY. The analyzer consists of three sections: Native PHY Debug Link Tuning Debug Dynamic Reconfiguration Debug Use this fault tree analyzer to help you resolve Transceiver PHY issues and bring up your design as efficiently as possible. Use it along with the Arria® 10 Device Transceiver PHY Debug Tool Download User Guide Arria® 10 Device Transceiver PHY Debug Tool This debug tool consists of the same four sub-tools as the Stratix® 10 version: Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register Eye debug tool enables you to measure the eye height and/or eye width Use this tool to analyze the health of the transceiver channels in your Arria® 10 Device. Additional Resources Topic Agilex™ 7 Agilex™ 5 Agilex™ 3 Quartus® Prime 1 Stratix® 10 Arria® 10 Cyclone® 10 Intellectual Property (IP) Core Release Notes E-Tile Dynamic Reconfiguration Design Example Release Notes F-Tile Auto-Negotiation and Link Training for Ethernet FPGA IP Release Notes F-Tile Dynamic Reconfiguration Suite FPGA IP Release Notes F-Tile PMA and FEC Direct PHY Multirate FPGA IP Release Notes F-Tile PMA/FEC Direct PHY IP Release Notes GPIO FPGA IP Release Notes GTS PMA/FEC Direct PHY IP Release Notes LVDS SERDES FPGA IP Release Notes GPIO FPGA IP Release Notes GTS PMA/FEC Direct PHY IP Release Notes LVDS SERDES FPGA IP Release Notes Quartus® Prime Design Suite Release Notes FPGA Device Errata Stratix® 10 GX L-Tile Production Device Errata Stratix® 10 SX Production Device Errata Arria® 10 GX/GT Device Errata and Design Recommendations Arria® 10 SX Device Errata and Design Recommendations Cyclone® 10 GX Device Errata and Design Guidelines User Guides (Refer to the chapter on debug functions in the following user guides) E-Tile transceiver PHY user guide F-Tile Architecture and PMA and FEC Direct PHY IP User Guide F-Tile Dynamic Reconfiguration Suite FPGA IP User Guide F-Tile PMA and FEC Direct PHY Multirate FPGA IP User Guide PHY Lite for Parallel Interfaces FPGA IP User Guide PHY Lite for Parallel Interfaces FPGA IP User Guide GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs Quartus® Prime Pro and Standard Software User Guides Stratix® 10 L- and H-Tile Transceiver PHY User Guide Arria® 10 Transceiver PHY User Guide Cyclone® 10 GX Transceiver PHY User Guide Transceiver Registers Mapping Guide F-Tile PMA and FEC Direct PHY FPGA IP Register Map GTS PMA/FEC Direct PHY IP Register Map GTS PMA/FEC Direct PHY IP Register Map for Agilex™ 3 Logical View of the Stratix® 10 L- and H-Tile Transceiver Registers Logical View of the Arria® 10 Transceiver Registers Logical View of the Cyclone® 10 Transceiver Registers Notes: Transceiver Native PHY IP Release Notes are now found within Quartus® Prime Design Suite Release Notes. Knowledge Base Solution Search the Knowledge Base for Agilex™ Devices Search the Knowledge Base for Stratix® 10 Devices Search the Knowledge Base for Cyclone® 10 GX Devices Search the Knowledge Base for Cyclone® 10 LP Devices Search the Knowledge Base for Arria® 10 Devices - 2026-03-10