** Error: ../<ip_naming>/fifo_<random string>/sim/<ip_naming>_fifo_<random string>_<random string>.vhd(31): near ")": (vcom-1576) expecting IDENTIFIER. - ** Error: ../<ip_naming>/fifo_<random string>/sim/<ip_naming>_fifo_<random string>_<random string>.vhd(31): near ")": (vcom-1576) expecting IDENTIFIER. Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, you might see this error while compiling the simulation files in the Questa*- FPGA Edition simulator. This error occurs when compiling the FIFO FPGA IP simulation model generated in VHDL. The error arises from a semicolon present at the end of the last port inside the entity (line 30) of the simulation files. Resolution To work around this problem, use one of the following steps: Generate the FIFO FPGA IP simulation model in Verilog HDL instead of VHDL. Or Remove the semicolon located on line 30 in the simulation files. The VHDL file can be found at: <project_directory>/<ip_naming>/fifo_<random string>/sim/<ip_naming>_fifo_<random string>_<random string>.vhd You need to remove it each time the simulation model is generated. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.4. Custom Fields values: ['novalue'] Troubleshooting 15014323648 False ['FIFO IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.3 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']