Why does my PLL output have an incorrect phase shift in the TimeQuest timing analyzer? - Why does my PLL output have an incorrect phase shift in the TimeQuest timing analyzer? Description Due to a problem in the Quartus® II software, the TimeQuest timing analyzer may calculate an incorrect phase shift for your PLL output clock. This problem occurs in Arria® V, Cyclone® V, and Stratix® V designs when you use derive_pll_clocks with a non-zero phase shift on the PLL reference clock. Resolution To work around this problem, perform one of the following actions: Use the phase shift setting on output clock instead of phase shifting the reference clock in your PLL. Constrain the PLL outputs using the create_generated_clock constraint instead of using derive_pll_clocks. Related Articles Why does derive_pll_clocks fail to automatically constrain PLL output clocks? Warning (332174): Ignored filter at <filename>.sdc: <hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco1ph[0] could not be matched with a pin How do I constrain PLL clocks when using clock switchover in 28-nm devices? Custom Fields values: ['novalue'] Troubleshooting 2205829605 False ['PLL'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']