Why does my Stratix® V Hard IP for PCI Express in Gen3 configuration fail to link up to L0 after toggling pin PERST in simulation? - Why does my Stratix® V Hard IP for PCI Express in Gen3 configuration fail to link up to L0 after toggling pin PERST in simulation? Description When simulating Stratix® V and Arria® V GZ Hard IP for PCI Express® as an Endpoint, the PCIe Hard IP can become stuck at Speed. Recovery if the Hard IP is reset after linking up to Gen3 L0. This is a known issue in the simulation model and has no impact on hardware. Resolution The issue will be fixed in a future Quartus® II software release. Custom Fields values: ['novalue'] Troubleshooting 84425 False ['PCI Express', 'Simulation'] ['novalue'] novalue novalue ['Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']