SEU Mitigation in Altera® FPGA Devices: Fault Injection - 14 Minutes As cloud-based services continue to grow, protection of that cloud data is even more important, such that single event upsets (SEU) are not just the concern of avionics and safety critical systems. With that in mind, this online training, SEU Mitigation in Altera® FPGA Devices: Fault Injection, discusses how to set up your Altera® FPGA design to perform hardware simulations of SEUs. In this training, you get a brief review of the SEU features that exist for certain Altera® FPGA devices. You then learn about fault injection and how it relates to Altera® FPGA devices. You learn about the Fault Injection, Error Message Register, and Advanced SEU Detection IP cores. Finally, you learn about the Fault Injection Debugger software and how it works with the IP cores. Course Objectives At course completion, you will be able to: Enable Altera® Arria® 10 and Altera® Cyclone 10 GX device features to reduce your Failures in Time (FIT) rate and to develop a SEU fault response solution Employ the Error Message Register IP core to help mitigate SEUs Employ the Advanced SEU Detection (ASD) IP core to improve your fault response by filtering SEU events Employ the Fault Injection IP core to communicate with the Fault Injection Debugger software Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus® Prime design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OSEUFAULT. FPGA_OSEUFAULT. <p>SEU Mitigation in Altera FPGA Devices: Fault Injection</p>