What are the maximum and minimum clock frequencies when driving the EDCRC block from user logic? - What are the maximum and minimum clock frequencies when driving the EDCRC block from user logic? Description The following application notes describe how to use error detection cyclic redundancy check (CRC): AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (PDF) AN 539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices (PDF) When you use the error detection block, you are required to provide a clock to the clk port. For the maximum and minimum error detection frequencies, refer to the SEU Mitgation chapter in the respective device handbook. Although those frequencies describe the internal oscillator, they are also applicable for the clk port. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Stratix® FPGAs', 'Stratix® GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']