Why does the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core fail to simulate using Cadence* NCSim and Xcelium when the RS-FEC is enabled? - Why does the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core fail to simulate using Cadence* NCSim and Xcelium when the RS-FEC is enabled? Description Due to a problem with the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core in RS-FEC mode, simulation will fail in both Cadence* NCSim and Xcelium. An Error similar to the one shown below will be seen: ncsim: *F,NOSNAP: Snapshot 'basic_avl_tb_top' does not exist in the libraries. Resolution To work around this problem, please use Synopsys* VCSMX or disable the RS-FEC. This problem is not scheduled to be fixed in a future release of the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting 2205894092 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']