Why does the Intel® Quartus® II software incorrectly show Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus® II v13.1 with a preliminary timing model and constraints..? - Why does the Intel® Quartus® II software incorrectly show Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus® II v13.1 with a preliminary timing model and constraints..? Description Due to a problem in the Quartus® II software version 13.1 Update 3 and later, you may see the following critical warnings when compiling a Cyclone® V SoC HPS design. Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus II v13.1 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing mode The timing models are final for the Cyclone® V SoC devices as listed in the ACDS version 13.1 Update Release Notes: Altera Complete Design Suite Version 13.1 Update Release Notes Resolution It is safe to ignore this critical warning. Custom Fields values: ['novalue'] Troubleshooting 187967 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.1 ['Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']