Why does the "Show PCIe Hard Interface Pins" option in the pin planner for the Cyclone® V GX (5CGXFC5C6U19A7) device variant highlight PIN R16 (nPERST0) for a PCIe Hard IP located in the bottom transceiver bank? - Why does the "Show PCIe Hard Interface Pins" option in the pin planner for the Cyclone® V GX (5CGXFC5C6U19A7) device variant highlight PIN R16 (nPERST0) for a PCIe Hard IP located in the bottom transceiver bank? Description Due to a problem in the Quartus® II software version 13.1 update 4 and later, the "Show PCIe Hard Interface Pins” for the Cyclone® V GX (5CGXFC5C6U19A7) incorrectly shows PIN R16 (nPERSTL0)as being associated with the PCIe® Hard IP located in the bottom transceiver bank. Resolution The correct pin location for the Hard IP located in the bottom transceiver bank is PIN R17 (nPERSTL1) Custom Fields values: ['novalue'] Troubleshooting 2205732612 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.1.4 ['Cyclone® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']