How to handle the input port cfglink2csrpld of the SV PCIe HIP? - How to handle the input port cfglink2csrpld of the SV PCIe HIP? Description The port cfglink2csrpld is an undesired port in the HIP variation file. In the SV PCIe user guide there're no any descriptions regarding this signal. Resolution You can connect the port cfglink2csrpld to "0" in your design. This port will be removed in Quartus II 12.0. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']