Why are there intermittent calibration failures in the External Memory Interfaces Agilex® 5 FPGA E-Series IP? - Why are there intermittent calibration failures in the External Memory Interfaces Agilex® 5 FPGA E-Series IP? Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you may run into intermittent EMIF calibration failures on LPDDR4 1CHx32, 2-Rank configurations running at 1333 MHz on Agilex® 5 FPGA E Series devices. Resolution To work around this problem, disable cross-rank delay averaging by enabling the following debug flag in the parameter table: DBG_CFG_DISABLE_RANK_AVG_AND_OVR This prevents the firmware from averaging DQS-WR delays across ranks, which eliminates the invalid delay setting that causes the MGN-stage calibration failure. Note: Disabling rank averaging may affect traffic stability in some configurations. A patch is available to fix this problem in Quartus Prime Pro Edition Software version 25.3.1. Download and install the below 1.04 patch. This problem has been fixed beginning with version 26.1 of the Quartus Prime Pro Edition Software. Custom Fields values: Troubleshooting QS-8943 novalue ['Memory Controllers'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 26.1 25.3.1 ['Agilex® 5 FPGAs and SoCs']