Can I assign transceivers' REFCLK pin to a general purpose PLL in Stratix II GX and Stratix IV GX/GT devices? - Can I assign transceivers' REFCLK pin to a general purpose PLL in Stratix II GX and Stratix IV GX/GT devices? Description You can assign transceivers' REFCLK pin as an input clock to a general purpose PLL in Stratix ® II GX and Stratix IV GX/GT devices, only if you have instantiated at least one transceiver channel within the block associated with that REFCLK pin. You can instantiate a dummy transceiver channel to use this REFCLK pin and keep the dummy transceiver channel in reset state during normal operation. This information also applies to other GX/GT/GZ device families with dedicated high speed transceivers/REFCLK pins. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['novalue'] novalue novalue ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V SX FPGA', 'Stratix® GX FPGA', 'Stratix® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']