Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Description You may see the critical warning above during the fitter stage when compiling the UniPHY-based memory controller IP. Resolution You may safely ignore this critical warning message. Custom Fields values: ['novalue'] Troubleshooting novalue False ['DDR3 SDRAM Controller with UniPHY IP'] ['novalue'] novalue novalue ['Stratix® III FPGAs'] ['novalue'] ['novalue'] ['novalue']