Quartus II Compile Failure for VIP Clocked Video Output (CVO) Core due to Undeclared Variable - Quartus II Compile Failure for VIP Clocked Video Output (CVO) Core due to Undeclared Variable Description The Quartus II software compiles failure for VIP CVO core due to undeclared variable. Affected ConfigurationHappens only if Video in and out use the same clock option is enabled. Design Impact Error (10207): Verilog HDL error at alt_vipitc111_IS2Vid.v(934): can’t resolve reference to object “rst_vid_clk_reg ” . Customer cannot compile the core successfully in the Quartus II software. Resolution Open the source file, alt_vipitc111_IS2Vid.v file. You can find this file under QUARTUS_ROOTDIR/../ip/altera/clocked_video_ip/src_hdl . Open the file, and go to line 934, or the line that contains the following “ .aclr(rst_vid_clk_reg) ” SDI configuration. Edit this line by removing the “ _reg ”, making the line as “ /aclr(rst_vid_clk )” Run and compile This issue will be fixed in a future version of VIP MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']