Low Latency Ethernet 100G MAC and PHY FPGA IP - Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Arria® V GZ FPGA Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Stratix® V GS FPGA Stratix® V GX FPGA Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional Forward Error Correction (FEC) block. It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Stratix and Arria FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules. The IP core is designed to the IEEE 802.3ba-2010 High-Speed Ethernet Standard, available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, supports full wire line speed with a 64-byte frame length, and supports back-to-back or mixed length traffic with no dropped packets. All Low Latency 100G Ethernet IP core variations include full-duplex MAC and PHY components. Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Low Latency Ethernet 100G MAC and PHY FPGA IP Key Features Soft PCS logic that interfaces seamlessly to Stratix 10 FPGA 25.78125 Gbps serial transceivers Offering Brief No No No Yes Encrypted Verilog Arria® V GZ FPGA Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes Offering Brief Production a1JUi0000049UV1MAM What's Included Encrypted Verilog source code Ordering Information IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF Digikey Mouser a1JUi0000049UV1MAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-08-28T18:42:48.000+0000 Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block. Altera Solutions