Can I manually instantiate Qsys Translator IP in a Qsys system? - Can I manually instantiate Qsys Translator IP in a Qsys system? Description Due to a problem in the Quartus® Prime software version 16.1 and earlier AXI, Avalon MM and APB Translator IPs are visible in the Quartus Prime software Qsys IP Catalog window under Qsys Interconnect / Memory-Mapped section. Translator IPs should not be manually added to Qsys systems, Qsys will add them automatically to generate system interconnect. Resolution This problem is due to be fixed in a future version of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 414148; False ['APB Translator IP', 'AXI Translator IP', 'Avalon-MM Master Translator IP', 'Avalon-MM Slave Translator IP', 'Altera® FPGA Interconnect'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']