Arria 10 - EMIF dual port access - Arria 10 - EMIF dual port access Dear community, I am working on Arria 10 plateform (Terasic HAN Pilot) to perform acquisition from external ADC at 250MSPS - 16 bits. Until now, I had a small "On-chip memory" 50kB to temporarily store data on FPGA side, dual-port, which was accessible from HPS side through h2f-lw bridge (and avalon-mm host) to read data, aswell as from an designed IP that writes data on this memory. Now I want to use DDR4 available memory (FPGA side) to write and read data in the same way. I know that I need an EMIF with avalon-mm slave, however I cannot see dual port access for EMIF ? Can I directly connect EMIF to both masters ? More general question would be then, does avalon-mm allows and works if you have 2 masters connected to a single slave ? Thanks for suggestion and clarification, Roman Replies: Re: Arria 10 - EMIF dual port access Assuming you use Platform Designer to implement the design, arbitration logic for multiple hosts (masters) to access a single agent (slave) will be included in the interconnect.