Why are my Input Delay Chain assignments not correctly reflected in the Timing Analyzer when using Intel® Arria® 10 and Intel® Cyclone® 10 GX devices? - Why are my Input Delay Chain assignments not correctly reflected in the Timing Analyzer when using Intel® Arria® 10 and Intel® Cyclone® 10 GX devices? Description To ensure the user assigned Input Delay Chain settings for I/O are reflected in the Timing Analyzer, follow these steps in the Resolution section. Resolution Enable the Fast Input register for the respective pins in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. Custom Fields values: ['novalue'] Troubleshooting 18010844320 False ['Generic Component'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']