Error May Occur When Generating Hard Memory Controller in Qsys - Error May Occur When Generating Hard Memory Controller in Qsys Description This problem affects DDR2 and DDR3 interfaces using the hard memory controller in Arria V or Cyclone V devices. When using Qsys to generate an Arria V or Cyclone V external memory controller, you might encounter the following error message during the Quartus II fitter phase: Error (15332): Port SHIFTEN of cyclonev_pll_reconfig "<module>:<instance>|<memory_module>_pll0:pll0|pll1~PLL_RECONFIG" has 10 connections, but the maximum bus width of port SHIFTEN is 9.. The error message occurs when the pll_sharing conduit of an external memory interface is exposed to a top-level conduit in Qsys. Qsys currently issues an incorrect warning, advising you to export the pll_sharing conduit to a top-level port. When you export the conduit, it prevents these signals from being trimmed correctly by the fitter because they are assigned to top-level pins. The fitter error then occurs. Resolution The workaround for this issue is to ignore the Qsys warning and to not export the conduit to a top-level port. The fitter error then should not occur. For additional information, refer to the following Knowledge Base solution: Why do I see a Qsys warning for the pll_sharing conduit even when the PLL sharing mode option is set to \'No Sharing\' in the UniPHY Megacore settings?� This issue will be corrected in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']