Why can Intel® Arria® 10 External Memory Interface (EMIF) not access the MMR slave port? - Why can Intel® Arria® 10 External Memory Interface (EMIF) not access the MMR slave port? Description Due to EMIF IP internal access to MMR resister in the calibration phase, this read valid asserting can be seen from the MMR slave port. This behavior will cause hanging up the access when the user connects the MMR slave port and Avalon MM master through the Avalon MM clock crossing bridge. Resolution Related Articles Here are related KDB solutions. https://www.intel.com/content/www/us/en/support/programmable/articles/000085925 Custom Fields values: ['novalue'] Troubleshooting FB: 432146; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 18.1 17.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']