Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_lvds_cv.cpp, Line: 2420 - Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_lvds_cv.cpp, Line: 2420 Description Due to a problem in the Quartus® II software version 12.0, you may see this internal error if your design implements an ALTLVDS_TX megafunction with the tx_outclock signal driving core logic. This internal error occurs for designs targeting Arria® V or Cyclone® V devices. Resolution Using the tx_outclock signal to drive core logic is unsupported. The Quartus II software begining with version 12.1 reports an error message describing the problem instead of producing an internal error. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']