SerialLite III Streaming MegaCore Function User Guide Omits Two Signals - SerialLite III Streaming MegaCore Function User Guide Omits Two Signals Description The SerialLite III Streaming MegaCore Function User Guide v14.0 erroneously omits mention of the following two signals. reconfig_to_xcvr Input Width: Source IP core and duplex IP core: 140 x N; Sink IP core: 70 x N. Clock domain: phy_mgmt_clk Description: Dynamic reconfiguration input for the hard transceiver in Arria V GX and Stratix V devices. N is the number of lanes. reconfig_from_xcvr Output Width: Source IP core and duplex IP core: 92 x N; Sink IP core: 46 x N. Clock domain: phy_mgmt_clk Description: Dynamic reconfiguration output for the hard transceiver in Arria V GX and Stratix V devices. N is the number of lanes. Resolution This issue has no workaround. If your SerialLite III Streaming IP core variation targets an Arria V GX device or a Stratix V device, you must ensure you connect these two signals in your design. This issue is fixed in version 14.0 Arria 10 Edition of the SerialLite III Streaming MegaCore Function User Guide . Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0a10 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25