Is there a known problem with how the Intel® Quartus® Prime Pro Edition Software implements Differential SSTL and HSTL I/O in Intel® Stratix® 10 devices? - Is there a known problem with how the Intel® Quartus® Prime Pro Edition Software implements Differential SSTL and HSTL I/O in Intel® Stratix® 10 devices? Description Yes, due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 17.0 or later, Differential SSTL and HSTL inputs might not sample the input signal when implemented on bi-directional I/O in Intel® Stratix® 10 devices if the respective VREF pin is not connected to a voltage reference. Differential SSTL and HSTL inputs should not require a VREF. Resolution This problem is fixed starting from the Intel® Quartus® Prime Pro Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507045879 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 17.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']