Can I use Intel Agilex® 7 FPGA I-Series, R-Tile I_PIN_PERST_N, and REFCLK_GXR dedicated Hard IP pins in my FPGA fabric design? - Can I use Intel Agilex® 7 FPGA I-Series, R-Tile I_PIN_PERST_N, and REFCLK_GXR dedicated Hard IP pins in my FPGA fabric design? Description No, you cannot use Intel Agilex® 7 FPGA I-Series, R-Tile I_PIN_PERST_N , and REFCLK_GXR dedicated Hard IP pins in your FPGA fabric design. The I_PIN_PERST_N_GXR and REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]P/N dedicated pins connect only to the R-Tile Hard IP silicon. They do not connect to the FPGA fabric. If you try to use the R-Tile dedicated Hard IP pins in your FPGA fabric design using the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, you might see the following internal error: Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp, Line: 1357 IC edge from src atom FALCONMESA_IO_IBUF:OUT (Id: 2282, with associated RE_GID: None) to dst atom FALCONMESA_FF:ACLR (Id: 610, with associated RE_GID: 4294967295) has zero delay when not expected and is not routed (edge from src 22292 <signal_name> to dst 14055 <user_signal_name>) Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp, Line: 1357 IC edge from src atom FALCONMESA_IO_IBUF:OUT (Id: 2268, with associated RE_GID: None) to dst atom NADDER_LCELL_COMB:DATAF (Id: 2342, with associated RE_GID: 4294967295) has zero delay when not expected and is not routed (edge from src 22145 <user_signal_name> to dst 22200 <user_signal_name>) Resolution To fix this problem, disconnect your FPGA fabric design from the I_PIN_PERST_N_GXR and REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]P/N pins. Custom Fields values: ['novalue'] Troubleshooting 18017619900 False ['PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']