What is the adaptive synchronization feature support plan for the DisplayPort Intel® FPGA IP core? - What is the adaptive synchronization feature support plan for the DisplayPort Intel® FPGA IP core? Description Below is the Adaptive Synchronization feature support plan by Intel® Quartus® Prime Pro Edition Software and Standard Edition Software. For DisplayPort Source implementation, refer to the DisplayPort Intel® FPGA user guide documentation and Video Input Feature Comparisons table to enable the adaptive synchronization feature. For DisplayPort Sink implementation, refer to the Design Example Variant table and the Intel® Stratix® 10 DisplayPort SST Parallel Loopback with AdaptiveSync Support section in DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide to enable the adaptive sync feature in the DPCD register. Resolution Refer to the table below for the DisplayPort Intel® FPGA IP core Adaptive Synchronization support plan. Custom Fields values: ['novalue'] Troubleshooting 1507111973 False ['DisplayPort'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 17.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']